Power semiconductor device

ABSTRACT

A device includes an array of cells, the source regions of the individual cells comprising a plurality of source region branches each extending towards a source region branch of an adjacent cell, the base regions of the individual cells comprising a corresponding plurality of base region branches merging together to form a single base region surrounding the source regions. The junctions between the merged base region and the drain region define rounded current conduction path areas for the on-state of the device between adjacent cells. Floating voltage regions of opposite conductivity type to the drain region are buried in the substrate beneath the merged base region. The features of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths of respective cells. The floating voltage regions include respective islands situated within the current conduction paths.

FIELD OF THE INVENTION

This invention relates to a power semiconductor device and moreparticularly to a power semiconductor device comprising an array ofcells distributed over a surface of a substrate, each cell having asource region formed at the substrate surface and surrounded in thesubstrate by a base region. A power semiconductor device of this kind isthe subject of European patent specification EP 02 291 458.4.

BACKGROUND OF THE INVENTION

Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor FieldEffect Transistors) are used in power electronics applications due totheir appreciable current carrying and off-state voltage blockingcapability with low on-state voltage drop. In terms of industrialapplications, power MOSFET devices are commonly used in many electronicsfields such as portable electronics, power supplies, telecommunicationsand, especially, in many industrial applications relating to automotiveelectronics, particularly, but not exclusively, as switching devices.

Typically, a power MOSFET has a structure extending in the depth of asubstrate in which a source, a base surrounding the source and a drainare of alternating p-type and n-type doping and an insulated gate layeris provided at the surface of the substrate. If the source and drain aren-type, and the base is p-type, for example, by applying a voltagehigher than a threshold level which biases the gate positive withrespect to the source, an n-type inversion layer or channel will beformed under a gate oxide insulating layer between the surface of thesubstrate and the gate thus forming an electrical connection between thesource and the drain regions and allowing a current to flow in an onstate of the device. Once the device is turned on, the electricaldrain-source resistance is referred to as the on-state resistance(R_(DSON)) and should be as low as possible, especially in a switchdevice. High cell density vertical insulated gate FET (IGFET) devices,for example, with a cell density of several hundred thousand cells/cm²,offer a particularly low on-state resistance per unit area at a low unitcost.

In the off-state, the voltage blocking capability is limited by thebreakdown voltage. Typically, the design of a MOSFET device addressesthe electrical isolation issue by arranging for each base cell region tobe electrically isolated in an epitaxial layer. Ideally, all baseregions should be at the same electrical potential in order to get agood snap back immunity while improving the breakdown voltage, likewiseincreasing the unclamped inductive switching (referred to as UIS)capability. To a large extent, the parameters favourable to highbreakdown voltage are unfavourable to low on-state resistance.

Generally speaking, a need exists for further improving the compromisebetween on-state resistance and breakdown voltage, with a goodelectrical contact to a unique base region so as to guarantee the highenergy capability (UIS), which need patent specification EP 02 291 458.4addresses.

US patent specification U.S. Pat. No. 6,037,632 describes a MOSFETdevice in which, within the drain region of the substrate and parallelto its surface, a layer of opposite conductivity type is buried,comprising a plurality of strips functioning as current paths and set ata potential different from the electrodes of the device when a depletionlayer reaches them.

Other semiconductor devices also are subject to compromises betweenon-state resistance and breakdown voltage. For example, internationalpatent specification WO 01 78152 describes a Schottky diode device inwhich islands of opposite conductivity type are buried in a layer of asubstrate in ‘beds’ spaced apart in the thickness of the layer. Thearticle “Ultra Low On-Resistance SBD with P-Buried Floating Layer” byWataru Saitoh, Ichiro Omura, Ken'ichi Tokano, Tsuneo Ogura and HiromichiOhashi published by the IEEE under the reference 0-7803-7357-X/02/$17.002002 IEEE also describes a Schottky barrier diode (SBD) structure with aburied electrically floating layer of opposite conductivity type and inthe form of stripes or dots.

However, it is found that, in each of these cases, the solution proposedis sub-optimal as regards breakdown voltage.

SUMMARY OF THE INVENTION

The present invention provides a power semiconductor device as describedin the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of individual cells during manufacture of a powersemiconductor device in accordance with one embodiment of the invention,given by way of example, before a base region merge operation,

FIG. 2 is a top view of individual cells during manufacture of a powersemiconductor device in accordance with another embodiment of theinvention, given by way of example, after a base region merge operation,

FIG. 3 is a top view of individual cells of the power semiconductordevice of FIG. 2 after the base region merge operation,

FIG. 4 is a simplified cross-sectional view of a portion of the powersemiconductor devices taken along lines A-A of FIG. 1 and FIG. 2 showingthe merged base region,

FIG. 5 is a simplified cross-sectional view of a portion of the powersemiconductor devices taken along lines B-B of FIG. 1 and FIG. 2,

FIG. 6 is a simplified cross-sectional view taken along lines C-C ofFIG. 1 and FIG. 2 of a portion of the power semiconductor devices,

FIG. 7 is an enlarged cross-sectional view taken along lines C-C of FIG.1 and FIG. 2 showing the structure of a substrate in the powersemiconductor devices,

FIG. 8 is a schematic perspective view of a section of the substrateshowing current flow in an embodiment of the invention, and

FIG. 9 is a perspective cut-out view of an element comprising adjacentparts of four adjacent cells in the device of FIG. 3, with detailedscrap perspective views of parts of the cells.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although in the following description the layers and regions will bedescribed as having certain conductivity types and being composed ofcertain materials, it will be appreciated that this is done by way ofexample only. The invention is applicable to other conductivity typesand to other materials than those specifically referred to herein.

FIG. 1 depicts in more detail a top view of individual cells of asemiconductor device according to an embodiment of the present inventionat a stage in the manufacturing process before a merge operation. Thecells are distributed over a surface of a substrate in an array, eachcell having a source region formed at the substrate surface, a baseregion surrounding the source region in the substrate and a drain regionsurrounding the base region. This arrangement provides high channeldensity and low on-state resistance.

As is shown in FIG. 1, in this embodiment of the invention, the array isa rectangular array in which the cells are disposed in rows and columns.The source and base regions of each individual cell have four branches80 each extending laterally outwards towards a similar branch 80 of anadjacent cell, the source region branches of adjacent cells presentingjuxtaposed ends. The four branches of each individual cell are arrangedso as to form the shape of a cross in this particular implementation butin other implementations a different number of radially extendingbranches are arranged differently.

The insulated gate comprises a polysilicon layer 32 insulated by anoxide layer (not seen in FIG. 1). A middle portion 34 of the device isshown in FIG. 1 with the insulated gate 32 removed, the lines in themiddle portion 34 indicating transitions in dopant conductivity typesuch as from P-type to N-type or vice-versa. Each branch 80 of the cellincludes a source region 37 within a separate base region 36 at thisstage of the manufacturing process.

The base region 36 is a P-conductivity doped region in a semiconductormaterial that is used to provide a current channel, this structure beingapplicable to devices of the MOSFET, IGFET or an IGBT kinds. The currentchannel is controlled by the overlying insulated gate layer 32.

The drain region is common to all the cells of the array and extendslaterally around and beneath the base regions 36. Instead of having aconfiguration where channels of individual cells are formed between theedge of source region 37 in the branches and the junction of base region36 and common drain region, the semiconductor device of this embodimentof the present invention, like the devices described in patentspecification EP 02 291 458.4, is configured so that the individualcells are aligned in an array with their base regions 36 connected toeach other by a merge operation of adjacent PHV regions adjacent andbetween the juxtaposed ends of the branches 80 to form a single baseregion surrounding the source regions of the individual cells of thearray in the substrate underneath the insulated gate 32. Merged baseregions 36 referred to as the P High Voltage are also called the PHV orbody regions.

More specifically, the source region branches of each cell each extendlaterally outwards towards at least one source region branch of anadjacent cell, the source region branches of adjacent cells where theypresent juxtaposed ends. The base regions of the individual cells of thearray comprise a corresponding plurality of base region branches eachextending laterally outwards towards at least one base region branch ofan adjacent cell, and the base region branches of adjacent cells aremerged together adjacent and between the juxtaposed ends of the sourceregion branches to form a single base region surrounding the sourceregions in the substrate.

In this embodiment of the invention, the four branches 80 of eachindividual cell are straight and are linked to each other by foursegments 41, which are straight in the embodiment of FIG. 1 and areconcave curved segments in the embodiment of FIG. 2. The concave curvedsegments 41 of FIG. 2 enable the breakdown voltage capability of thedevice to be increased by reducing electrical field concentration atsharp radiuses and facilitating obtaining a substantially constantradius for the rounded area of the PHV body region 36.

The four branches 80 are arranged in such a way that they have a width44 that is less than width 43 which is the widest distance betweenradially opposed portions of insulated gate 32 even before the baseregion merge operation. Width 44 is the width of the source region 37 ineach branch 80.

It will be appreciated that the structural dimensions of the individualcells depend on the operating voltage design range. In a preferredembodiment, width 44 in each branch 80 is of the order of a few micronsor in a range from approximately 1 to 3.5 microns and width 43 betweentwo parallel segments is approximately 0.5 to 2 microns greater thanwidth 44. Each branch 80 has a length 46 less than 10 microns preferablyin a range from 2.5 to 5 microns. Each parallel branch 80 is spacedapart with a distance 47; in the device of European patent specificationEP 02 291 458.4, the distance 47 is in a range from approximately 3 to 7microns with 4 to 5 microns preferred, in an embodiment of the presentinvention, as described below, this distance can be increased, forexample to 8 microns. With these dimensions, insulated gate 32 can bewider than the width 44 of source region 37 in each branch 80.

In this embodiment of the invention, the branches 80 are preferablyformed in the insulated gate 32 after the insulated gate has beendeposited onto an underlying semiconductor material. After the fourbranches 80 are formed, the base region 36 is formed first followed bysource region not only in the enlarged central area 48 but also in thebranches 80. Both regions are formed by incorporating the appropriatedopant type (N-type or P-type) into the underlying semiconductormaterial.

Within each contact segment portion 41, doped contact regions 38 aresurface contact areas for the base region situated within the centralportion 48 of the source region that is within or bounded by contactsegment portions 41. Doped contact region 38 is for example heavilydoped P-type but generally with lighter dopant concentration than sourceregion 37, and base region 36 is a more lightly doped P-type region.

FIG. 3 shows a top view of individual cells of the device of FIG. 2after the merge operation within the adjacent base regions 36 betweenthe ends of branches 80. After the merge operation, the initial array ofseparate base or PHV regions form a single matrix of base regions 36whereas the laterally convex current conduction path areas 39 of thedrain region remain physically separated laterally at the substratesurface even though they interconnect beneath the cells and have thesame voltage applied to them. The merge operation between the adjacentbase regions 36 of the embodiment of FIG. 1 produces a generally similarstructure.

In the semiconductor device in accordance with the embodiments of thepresent invention described and shown in FIGS. 1 to 3, the specific cellopenings in the continuous polysilicon gate layer 32 form the sourceregion 37 and base regions, which base regions 36 are merged together bydiffusion under the ends of branches 80 and thus form a continuous baseregion 36. The single base region 36 surrounds the source regions 37 ofthe individual cells of the array in the substrate, with junctions thatlaterally are solely concave between the merged base region and thedrain region. The junctions define in the drain region rounded currentconduction path areas 39 for the on-state of the device between adjacentcells, as shown in FIGS. 4 and 5, the current conduction paths 39 beingdepleted in the off-state of the device to block flow of current betweenthe source regions and the drain electrode.

FIG. 4 represents a simplified cross-sectional view of a portion of asemiconductor device taken along line A-A of FIG. 1 between twojuxtaposed ends of branches of two adjacent individual cells. Only thelayers that are relevant to show the merged PHV regions resulting fromthe merging process of the PHV or base regions of each of the adjacenthorizontal branches are shown in FIG. 4. The merge of the PHV regions athigh temperature creates the contact continuity between all PHV regionsof all branches so as to form the matrix of merged PHV regions. Byhaving merged base or PHV regions, the phenomenon of parasitic NPN orPNP bipolarity (also called snap back effect) is avoided since the baseregion will always be polarised. Thus, the breakdown voltage is improvedas well as the Unclamped Inductive Switching (UIS) such that the voltageand the current circulating between the individual cells can besustained at a higher level.

This merge or diffusion is achieved by a process parameter optimisationin conjunction with the actual layout without requiring any extra masklayers. The merge or diffusion operation is performed in two steps: theimplant of the PHV and the merge or diffusion itself.

The implant of the PHV or the base region requires the use of a correctdoping dose. Once this step is completed, the process of merge ordiffusion can start involving 2 parameters: time and temperature. For amerge or diffusion which lasts between 1 to 2 hours at 1100° C., thestructural dimensions of the individual cells are such that for instancewidth 44 in each branch is between 1 to 3.5 microns. To some extent, thedoping dose employed during the implant of the PHV will also affect thestructural dimensions of the individual cells.

In another embodiment, instead of using masking and diffusion to obtaina single body region 36, another masking and implant step is added tomerge the adjacent body regions of adjacent individual cells. Thisenables more flexibility in the choice of the width of the contactregions of the cells and, particularly in the case of high stand-offvoltage devices, enables the contact continuity regions to be formedmerged with a high level of uniformity and well rounded corners at thejuxtaposed ends of the adjacent cell branches without needing a furtherdrive (or lateral diffusion) step.

FIG. 5 represents a simplified cross-sectional view of a portion of thesemiconductor device taken along line B-B of FIG. 1 and FIG. 2. As seenin FIG. 4, the merging process occurs at the position of the line A-Aadjacent and between the juxtaposed ends of each two adjacent branches80 of two adjacent individual cells whereas, as shown in FIG. 5, at theposition of the line B-B, there is no merging of the PHV regions betweentwo parallel branches of 2 adjacent individual cells.

FIG. 6 represents a cross-sectional view of a portion of the full depthof the semiconductor device taken along line C-C of an individual cellshowing additional layers that have been formed for a finished MOSFETdevice.

As is shown in FIG. 6, the MOSFET device includes a drain electrode 83,a semiconductor substrate 62 having a first surface 92 and secondsurface 94 parallel to the first surface and is configured to conductcurrent between the first surface and the second surface.

Substrate 62 typically includes a first substrate layer 63 having a highdopant concentration and a second substrate layer 64 formed on the firstsubstrate layer 63, the second layer 64 being of the same conductivitytype as the first substrate layer 63, but more lightly doped. Forexample, in an N-channel MOSFET device, the first substrate layer 63 andsecond substrate layer 64 have an N-type conductivity. In a P-channelMOSFET device, the first substrate layer 63 and second substrate layer64 have a P-type conductivity. Doped layer 64 has a dopant concentrationthat depends on the desired breakdown voltage characteristics of thefinished device. In this embodiment of the invention, the thickness ofthe second substrate layer 64 is in a range from approximately 1 to 10microns, for example. The second substrate layer 64 is formed using amethod described below. That portion of the second substrate layer 64around and below the base or PHV region 36 forms part of the commondrain region 39.

The base or PHV region 36 is formed from the first surface of substrate62 and extends to a depth 69 into substrate 62. Base or PHV region 36 isdoped with a dopant having opposite conductivity type to the secondsubstrate layer 64. For example, in a N-channel MOSFET device, base orPHV region 36 has a P-type conductivity. In a P-channel MOSFET device,base or NHV region 36 has an N-type conductivity. As mentioned earlier,NHV or PHV region 36 typically is referred to as the ‘high voltage’region because of its breakdown characteristics. In this embodiment ofthe invention, NHV or PHV region has a doping surface profile with adepth 69 in the range of 1 micron, for example.

The source regions 37 in the branches 80 and in the central area 48 areformed within and surrounded by the base or PHV region 36, and extend toa depth less than depth 69. In this embodiment of the invention, thesource regions have a depth in a range from 0.15 to 0.25 microns, forexample. As seen in FIG. 6 along line C-C of FIG. 1, source regionappears as having two portions within base or PHV region 36 because thecross-section is taken through the centre of one of contact segmentportions 41. Source region 37 is doped with a dopant having the sameconductivity type as the second substrate layer 64 and the firstsubstrate layer 63.

Within contact segment portions 41, doped contact regions 38 are formedand extend into base or PHV region 36 to a depth of less than about onemicron. Doped contact regions 38 are doped with a dopant having the sameconductivity type as base or PHV region 36, but are doped to a higherdopant concentration than base or PHV region 36.

Gate oxide layer 76 is formed over a portion of source region of thecentral area 48, a portion of base or PHV region 36, and doped layer 64.Gate oxide layer 76 typically comprises a silicon oxide, has a thicknessof several hundreds of angstroms depending on the operating voltage, andmay be formed using well-known techniques. By using suitable processingtechniques, insulated gate 32 is formed over gate oxide layer 76 andcomprises for example a doped polycrystalline semiconductor materialsuch as polysilicon.

Additional layers 78 are formed over insulated gate 32 using suitabletechniques, and typically comprise a dielectric such as silicon oxide.Optionally, these additional layers 78 comprises a multilayer such as asilicon nitride layer formed on insulated gate region 32 and a siliconoxide layer formed on the silicon nitride layer.

Preferably, gate oxide layer 76, insulated gate region 32, andadditional layer 78 are formed on substrate 62. The base or PHV region36 is then formed in doped layer 64 followed by source regions 37 in thebranches 80, using the layers produced as mask, as well as in thecentral area 48 and then doped contact region 38. The base or PHV region36, source regions 37 and doped contact regions 38 are formed using, forexample, ion implantation techniques.

A source ohmic layer or source electrode 82 is formed over theadditional layer 78 and contacts both source region 37 and doped basecontact region 38, short-circuiting the two together. Spacer regions 79,for example comprising silicon oxide, isolate source ohmic layer 82 fromthe insulated gate region 32. Spacer regions 79 may be formed bydepositing a silicon oxide layer followed by an unmasked etching processto provide the structure as is shown in this figure.

Source ohmic layer 82 may comprise a metal layer with or without abarrier layer. A passivation layer can be formed on top of the MOSFETdevice.

Common drain ohmic layer or drain electrode 83 is formed over the secondsurface of substrate 62 and typically comprises a multilevelmetallisation such as titanium/nickel/silver or the like. Arrows 86 showmore clearly how current flows from drain region 37 into the currentconduction paths 39 of the source region, the current then flowingthrough the drain region to the drain electrode 83.

As shown in FIGS. 7 and 9, the second substrate layer 64 includesfloating voltage regions of opposite conductivity type to the substrate,buried in the substrate 64 beneath the merged base region 36 andpresenting features 102 corresponding to and juxtaposed with features ofthe merged base region in each cell. In operation in the off-state, whenthe depletion layers blocking the current conduction paths 39 reach thefloating voltage regions 102, the voltage of the floating voltageregions is brought abruptly to the voltage of the source regions 37 bypunch-through; a new depletion layer then forms beneath and adjacent tothe floating voltage regions 102 whereby to enhance the development ofthe depletion layers in the drain region. Accordingly, the breakdownvoltage of the device in the off-state for the same dimensions, geometryand dopant concentrations is increased. In turn this enables a reductionin the on-state resistance, since the dopant concentration of the drainregion current conduction paths can now be increased while stillmaintaining a sufficient breakdown voltage. In summary, whatever thetrade-off chosen between off-state breakdown voltage and on-stateresistance by altering the various parameters, the overall compromiseperformance is improved by the addition of the floating voltage regions102.

In one embodiment of the invention, as shown in FIGS. 8 and 9, thefloating voltage regions 102 present features 104 whose lateral shape issimilar to the merged base regions 36, without necessarily beingidentical to them. In this embodiment, the features 104 are continuousand define rings of the opposite conductivity type to the drain regionthat surround the current conduction paths 39 between the adjacentcells.

In another embodiment of the invention, not shown in the drawings, thefloating voltage regions 102 present an array of separate features whoselateral shape is similar to the shape of the source regions 37 and ofthe base regions 36 before the merging operation, the separate featuresof each cell being buried in the substrate beneath the merged baseregion and juxtaposed with corresponding features of the merged sourceand base region in each cell. In this embodiment, the separate featuresof the floating voltage regions 102 of adjacent cells partially surroundthe current conduction paths 39 between the adjacent cells.

In addition, in these embodiments of the invention, the floating voltageregions 102 include islands or plugs 106 of the opposite conductivitytype to the drain region that are situated centrally within each of thecurrent conduction paths 39. While the islands 106 restrict somewhat thecross-sectional area of the current conduction paths 39, which tends toincrease the on-state resistance, they produce a much more significantincrease in the off-state breakdown voltage, making a considerablepositive contribution to the compromise between on-state resistance andoff-state breakdown voltage. In particular, the cell lateral dimensionsand especially the diameter of the current conduction paths 39 may beincreased, much more than compensating the restriction of thecross-sectional area of the current conduction paths 39 by the islands106 while still maintaining a sufficient breakdown voltage; for example,as shown in FIG. 8, the spacing 47 of adjacent cells may be 8 microns inthis embodiment of the invention.

In this embodiment of the invention, the layer 64 of the substrate infact comprises two layers 108 and 110, produced by successive steps ofepitaxial growth on the layer 63. The floating regions 102 extendadjacent to the interface between the layers 108 and 110. In thisembodiment of the invention, the floating regions 102 are produced bydepositing or implanting p-type dopant on the layer 108 before thesecond epitaxial growth step produces the layer 110, or by very highenergy implantation. Subsequent process steps cause the dopant at theinterface to diffuse into the layers 108 and 110 on each side of theinterface. It will be appreciated that the process parameters of allsuch subsequent process steps must be calculated and, if necessaryadjusted, to take account of their effect on the dopant diffusion of thefloating regions 102.

In one embodiment of the invention, as shown in FIG. 7, each of thecurrent conduction paths 39 includes, adjacent the interface, a furtherlayer 112 that is more lightly doped than the two layers 108 and 110 andis of the same conductivity type as the two layers 108 and 110. In theoff-state, the layer 112 brings the depletion layer in the currentconduction paths 39 deeper in the substrate and closer to the drainelectrode 83, hence increasing the breakdown voltage. Although theaddition of the lightly doped layer 112 tends to increase the on-stateresistance, it is arranged to be thin and the effect is small comparedwith the improvement obtained in breakdown voltage by its addition. Inone embodiment of the invention, the lightly doped layer 112 is producedby adjusting the parameters of deposition during the second epitaxialgrowth step. In another embodiment of the invention, the lightly dopedlayer 112 is produced by further epitaxial growth step prior to thesecond epitaxial growth step or by high energy implant

It will be appreciated that the cross-sectional configuration of thebase or PHV regions 36 can be modified to further enhance breakdownvoltage characteristics of MOSFET devices. For example, the branches 80of the individual cells may have various shapes as long as the baseregions of the adjacent individual cells can merge at and adjacentjuxtaposed ends of the respective branches without introducing convexlateral shapes at the base-drain junctions defining the currentconduction paths 39.

Also, instead of having four branches 80 in each cell extending atright-angles to each other, other configurations may be chosen; forexample each cell may have three branches extending at 120°, thebranches of the cells forming a network with hexagonal sides surroundingthe current conduction paths 39, like a honey comb. Alternatively, eachcell may have more than four branches. For instance, in a configurationof individual cells with six branches extending at 60°, the branches ofthe cells form a network with triangular sides surrounding the currentconduction paths 39.

1. A power semiconductor device comprising an array of cells, each cellof the array comprising a source region formed at the substrate surface,a base region surrounding said source region in the substrate, a drainregion underlying said source region and said base region, and a drainelectrode contacting said drain region, a plurality of branches eachextending laterally outwards towards at least one branch of an adjacentcell, the source regions in the branches of adjacent cells presentingjuxtaposed ends, the base regions in the branches of the individualcells of the array comprising a corresponding plurality of base regionbranches each extending laterally outwards towards at least one baseregion in a branch of an adjacent cell, and the base regions in thebranches of adjacent cells merging together adjacent and between saidjuxtaposed ends to form a single base region surrounding said sourceregions of the individual cells of said array in the substrate, withjunctions that laterally are solely concave between the merged baseregion and the drain region defining a portion of a rounded currentconduction path for the on-state of the device between adjacent cellsthat are depleted in the off-state of the device to block flow ofcurrent between the source regions and the drain electrode, and afloating voltage region of opposite conductivity type to said drainregion, buried in the substrate, extending beneath said merged baseregion and presenting a portion of a floating voltage feature and aportion of a floating island, the floating voltage regions of adjacentcells merge together to define the floating voltage feature completelysurrounding laterally said current conduction path, and wherein thefloating island is situation within said conduction path.
 2. A powersemiconductor device as claimed in claim 1, wherein said floatingvoltage regions extend adjacent an interface between two layers of saidsubstrate.
 3. A power semiconductor device as claimed in claim 2,wherein each of said current conduction paths includes, adjacent saidinterface, a further layer that is more lightly doped than said twolayers and is of a same conductivity type as said two layers.
 4. A powersemiconductor device as claimed in claim 2, wherein said two layers areepitaxial layers.
 5. A power semiconductor device as claimed in claim 3,wherein said two layers are epitaxial layers.
 6. A semiconductor devicehaving a plurality of cells arranged in an array, the device comprising:a portion of the plurality of cells form a two-dimensional array, eachcell of the two-dimensional array adjacent to each other cell of thetwo-dimensional array of cells, and each cell of the two-dimensionalarray comprising: a source region; a base region surrounding said sourceregion; a drain region underlying the source region and the base region;and a floating voltage region buried in said drain region and ofopposite conductivity type to said drain region, said floating voltageregion presenting a portion of a first floating voltage feature thatalong with first floating voltage regions of each other cell of thetwo-dimensional array completely surrounds laterally a first currentconduction path of said device for an on state.
 7. A semiconductordevice as claimed in claim 6, wherein said floating voltage regionadditionally presenting a portion of a first floating voltage islandsituated within said first current conduction path.
 8. A semiconductordevice as claimed in claim 7, wherein said floating voltage regionpresenting a portion of a second floating voltage feature thatcompletely surrounds laterally a second current conduction path of saiddevice for the on state, and said floating voltage region additionallypresenting a portion of a second floating voltage island situationwithin said second current conduction path.
 9. A semiconductor device asclaimed in claim 8, wherein said floating voltage region is mergedtogether with floating voltage regions of adjacent cells.
 10. A deviceas claimed in claim 6, wherein said source region is at a first majorsurface of a substrate.
 11. A device as claimed in claim 6, wherein saidsource region is at a first major surface of a substrate, and said drainregion includes a drain contact at a second major surface of saidsubstrate, said second major surface being located opposite and parallelto said first major surface.
 12. A device as claimed in claim 6, whereineach one of said base regions comprise a plurality of base branches,each base branch extending laterally outwards towards a base branch ofan adjacent cell and surrounding a corresponding source branch of saidsource region.
 13. A device as claimed in claim 12, wherein each basebranch is merged together with a corresponding base branch of anadjacent cell.
 14. A device as claimed in claim 6, wherein a firstportion of said drain region that is lateral to said floating voltageregion has a lighter doping concentration than a second portion and athird portion of said drain region, said first portion being locatedbetween said second portion and said third portion.
 15. A device asclaimed in claim 6, wherein each cell has a pitch of at leastapproximately 8 micrometers.
 16. A method of forming a semiconductordevice comprising a plurality of cells arranged in an array the methodcomprising: forming a two-dimensional array of cells from a portion ofthe plurality of cells, each cell of the two-dimensional array of cellsadjacent to each other cell of the two-dimensional array, and each cellof the two-dimensional array further formed by: forming a source region;forming a base region surrounding said source region; forming a drainregion underlying the source region; and forming a floating voltageregion buried in said drain region and of opposite conductivity type tosaid drain region, said floating voltage region presenting a portion ofa first floating voltage feature that along with first floating voltageregions of each other cell of the two-dimensional array completelysurrounds laterally a first current conduction path of said device foran on state.
 17. A method as claimed in claim 16 wherein said floatingvoltage region additionally presenting a portion of a first floatingvoltage island situated within said first current conduction path. 18.The device of claim 6, wherein the two-dimensional array is a two-by-twoarray.
 19. The method of claim 16, wherein the two-dimensional array isa two-by-two array.